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MC74LVX50 Hex Buffer
The MC74LVX50 is an advanced high speed CMOS buffer fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffered output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.
Features
http://onsemi.com MARKING DIAGRAMS
* * * * * * * *
High Speed: tPD = 4.1 ns (Typ) at VCC = 3.3 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2.0 V to 3.6 V Operating Range Low Noise: VOLP = 0.5 V (Max) Pb-Free Packages are Available*
14 14 1 SOIC-14 D SUFFIX CASE 751A 1 LVX50 AWLYWW
14 14 1 TSSOP-14 DT SUFFIX CASE 948G 1 LVX 50 ALYW
14 SOEIAJ-14 M SUFFIX CASE 965 1 1 74LVX50 ALYW
14
A WL or L Y WW or W
= = = =
Assembly Location Wafer Lot Year Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
March, 2005 - Rev. 3
Publication Order Number: MC74LVX50/D
MC74LVX50
A1 1 2 Y1
A2
3
4
Y2 A1
1 1 1 1 1 1
Y1 Y2 Y3 Y4 Y5 Y6
A3
5
6
Y3 Y=A
A2 A3
A4
9
8
Y4 A4
A5
11
10
Y5
A5 A6
A6
13
12
Y6
Figure 1. Logic Diagram
Figure 2. Logic Symbol
VCC 14
A6 13
Y6 12
A5 11
Y5 10
A4 9
Y4 8
FUNCTION TABLE
A Input L H Y Output L H
1 A1
2 Y1
3 A2
4 Y2
5 A3
6 Y3
7 GND
14-Lead Pinout (Top View)
ORDERING INFORMATION
Device MC74LVX50D MC74LVX50DG MC74LVX50DR2 MC74LVX50DR2G MC74LVX50DT MC74LVX50DTR2 MC74LVX50M MC74LVX50MG MC74LVX50MEL MC74LVX50MELG Package SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* SOEIAJ-14 SOEIAJ-14 (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) Shipping 55 Units / Rail 55 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 50 Units / Rail 50 Units / Rail 2000 Tape & Reel 2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74LVX50
MAXIMUM RATINGS
Symbol VCC VIN VOUT IIK IOK IOUT ICC TSTG TL TJ qJA DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink Current DC Supply Current per Supply Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature under Bias Thermal Resistance (Note 1) SOIC TSSOP VI < GND VO < GND Parameter Value *0.5 to )7.0 *0.5 to )7.0 *0.5 to VCC )0.5 *20 $20 $25 $50 *65 to )150 260 )150 125 170 Level 1 Oxygen Index: 30% - 35% Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Above VCC and Below GND at 85_C (Note 5) UL 94-V0 @ 0.125 in > 2000 > 200 2000 $300 V Unit V V V mA mA mA mA _C _C _C _C/W
MSL FR VESD
Moisture Sensitivity Flammability Rating ESD Withstand Voltage
ILatchup
Latchup Performance
mA
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm-by-1 inch, 2-ounce copper trace with no air flow. 2. Tested to EIA/JESD22-A114-A. 3. Tested to EIA/JESD22-A115-A. 4. Tested to JESD22-C101-A. 5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO TA Dt/DV Supply Voltage Input Voltage Output Voltage Operating Free-Air Temperature Input Transition Rise or Fall Rate VCC = 3.0 V $0.3 V (Note 6) (HIGH or LOW State) Parameter Min 2.0 0 0 *40 0 Max 3.6 5.5 VCC )85 100 Unit V V V _C ns/V
6. Unused inputs may not be left open. All inputs must be tied to a high- or low-logic input voltage level. NOTE: The qJA of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and figure below.
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MC74LVX50
IIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIIIII IIIIII IIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I IIIIIIIIIIIIIIIIIIIIII IIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I III I I I I I I IIIIIII IIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIII IIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I IIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIII IIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III III I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII I I
Symbol VIH Parameter Test Conditions VCC (V) 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.0 2.0 3.0 3.0 TA = 25C Typ TA 85C Min 1.5 2.0 2.4 Max Min 1.5 2.0 2.4 Max Unit V High-Level Input Voltage VIL Low-Level Input Voltage 0.5 0.8 0.8 0.5 0.8 0.8 V VOH High-Level Output Voltage (VIN= VIH or VIL) Low-Level Output Voltage (VIN= VIH or VIL) Input Leakage Current IOH = -50 mA IOH = -50 mA IOH = -4 mA 1.9 2.9 2.58 2.0 3.0 0.0 0.0 1.9 2.9 2.48 V VOL IOL = 50 mA IOL = 50 mA IOL = 4 mA 0.1 0.1 0.36 0.1 2.0 0.1 0.1 0.44 1.0 V IIN VIN = 5.5 V or GND VIN = VCC or GND 0 to 3.6 3.6 mA mA ICC Quiescent Supply Current 20.0
DC ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns
TA = 25C Typ 5.4 7.9 4.1 6.6
TA 85C
SymbolIIIIIIIII Parameter tPLH, tPHL Propagation Delay, Input A to Y
Test Conditions
Min
Max
Min 1.0 1.0 1.0 1.0
Max
Unit ns
VCC = 2.7 V
CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 50 pF
10.1 13.6 6.2 9.7 1.5 1.5 10
12.5 16.0 7.5 11.5 1.5 1.5 10
VCC = 3.3 V 0.3 V VCC = 2.7 V
tOSHL tOSLH CIN
Output-to-Output Skew (Note 7) (N Input Capacitance
ns
VCC = 3.3 V 0.3V
CL = 50 pF
4
pF
Typical @ 25C, VCC = 3.3 V 15
CPD
Power Dissipation Capacitance (Note 8)
pF
7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH); parameter guaranteed by design. 8. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3 V
TA = 25C Symbol VOLP VOLV VIHD VILD Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Typ 0.3 -0.3 Max 0.5 -0.5 2.0 0.8 Unit V V V V
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MC74LVX50
TEST POINT VCC A 50% GND tPLH 50% VCC Y *Includes all probe and jig capacitance tPHL DEVICE UNDER TEST OUTPUT CL *
Figure 3. Switching Waveforms
Figure 4. Test Circuit
INPUT
Figure 5. Input Equivalent Circuit
EMBOSSED CARRIER DIMENSIONS (See Notes 9 and 10)
Tape Size
8 mm
B1 Max
4.35 mm (0.179")
D
1.5 mm + 0.1 -0.0 (0.059" ( +0.004 0 004 -0.0)
D1
1.0 mm Min (0.179") 1.5 mm Min (0.060)
E
1.75 mm 0.1 (0.069 0.004") )
F
3.5 mm 0.5 (1.38 0.002") 5.5 mm 0.5 (0.217 0.002")
K
2.4 mm Max (0.094") 6.4 mm Max (0.252")
P
4.0 mm 0.10 (0.157 0.004") 4.0 mm 0.10 (0.157 0.004") 8.0 mm 0.10 (0.315 0.004") 4.0 mm 0.10 (0.157 0.004") 8.0 mm 0.10 (0.315 0.004") 12.0 mm 0.10 (0.472 0.004") 16.0 mm 0.10 (0.63 0.004")
P0
4.0 mm 0.1 (0.157 0.004") )
P2
2.0 mm 0.1 (0.079 0.004") )
R
25 mm (0.98")
T
0.6 mm (0.024)
W
8.3 mm (0.327)
12 mm
8.2 mm (0.323")
30 mm (1.18")
12.0 mm 0.3 (0.470 0.012")
16 mm
12.1 mm (0.476")
7.5 mm 0.10 (0.295 0.004")
7.9 mm Max (0.311")
16.3 mm (0.642)
24 mm
20.1 mm (0.791")
11.5 mm 0.10 (0.453 0.004")
11.9 mm Max (0.468")
24.3 mm (0.957)
9. Metric Dimensions Govern-English are in parentheses for reference only. 10. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10 within the determined cavity
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MC74LVX50
K t D TOP COVER TAPE P2
P0
10 PITCHES CUMULATIVE TOLERANCE ON TAPE 0.2 mm (0.008") E
A0 SEE NOTE 11 B1 K0 SEE NOTE 11 FOR MACHINE REFERENCE ONLY INCLUDING DRAFT AND RADII CONCENTRIC AROUND B0
F
W
+
B0 P
+
+
D1 FOR COMPONENTS 2.0 mm x 1.2 mm AND LARGER
EMBOSSMENT USER DIRECTION OF FEED
CENTER LINES OF CAVITY
*TOP COVER TAPE THICKNESS (t1) 0.10 mm (0.004") MAX. R MIN. TAPE AND COMPONENTS SHALL PASS AROUND RADIUS "R" WITHOUT DAMAGE
BENDING RADIUS
EMBOSSED CARRIER
EMBOSSMENT
10
MAXIMUM COMPONENT ROTATION TYPICAL COMPONENT CAVITY CENTER LINE
100 mm (3.937") 1 mm MAX
TAPE 1 mm (0.039") MAX
TYPICAL COMPONENT CENTER LINE
250 mm (9.843")
CAMBER (TOP VIEW) ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
11. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10 within the determined cavity
Figure 6. Carrier Tape Specifications
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MC74LVX50
t MAX
1.5 mm MIN (0.06") 20.2 mm MIN (0.795")
13.0 mm 0.2 mm (0.512" 0.008")
A
50 mm MIN (1.969")
FULL RADIUS
G
Figure 7. Reel Dimensions REEL DIMENSIONS
Tape Size 8 mm 8 mm 12 mm 16 mm 24 mm T&R Suffix T1, T2 T3, T4 R2 R2 R2 A Max 178 mm (7") 330 mm (13") 330 mm (13") 360 mm (14.173") 360 mm (14.173") G 8.4 mm, +1.5 mm, -0.0 (0.33" + 0.059", -0.00) 8.4 mm, +1.5 mm, -0.0 (0.33" + 0.059", -0.00) 12.4 mm, +2.0 mm, -0.0 (0.49" + 0.079", -0.00) 16.4 mm, +2.0 mm, -0.0 (0.646" + 0.078", -0.00) 24.4 mm, +2.0 mm, -0.0 (0.961" + 0.078", -0.00) t Max 14.4 mm (0.56") 14.4 mm (0.56") 18.4 mm (0.72") 22.4 mm (0.882") 30.4 mm (1.197")
DIRECTION OF FEED
BARCODE LABEL POCKET HOLE
Figure 8. Reel Winding Direction
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MC74LVX50
CAVITY TAPE
TOP TAPE
TAPE TRAILER (Connected to Reel Hub) NO COMPONENTS 160 mm MIN
COMPONENTS
TAPE LEADER NO COMPONENTS 400 mm MIN
DIRECTION OF FEED
Figure 9. Tape Ends for Finished Goods
User Direction of Feed
Figure 10. TSSOP and SOIC R2 Reel Configuration/Orientation
TAPE UTILIZATION BY PACKAGE
Tape Size 8 mm 12 mm 16 mm 24 mm 8-Lead 14-, 16-Lead 18-, 20-, 24-, 28-Lead 8-, 14-, 16-Lead 20-, 24-Lead 48-, 56-Lead 8-, 14-, 16-Lead 20-, 24-Lead 48-, 56-Lead SOIC TSSOP QFN SC88A / SOT-353 SC88/SOT-363 5-, 6-Lead
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MC74LVX50
PACKAGE DIMENSIONS
SOIC-14 D SUFFIX CASE 751A-03 ISSUE G
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE A
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 --- 1.20 --- 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
DIM A B C D F G H J J1 K K1 L M
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EEE CCC EEE CCC
MC74LVX50
PACKAGE DIMENSIONS
SOEIAJ-14 M SUFFIX CASE 965-01 ISSUE O
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
b 0.13 (0.005)
M
A1 0.10 (0.004)
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PUBLICATION ORDERING INFORMATION
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MC74LVX50/D

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